30 research outputs found
Dynamic reconfiguration technologies based on FPGA in software defined radio system
Get PDFPartial Reconfiguration (PR) is a method for Field Programmable Gate Array (FPGA) designs which allows multiple applications to time-share a portion of an FPGA while the rest of the device continues to operate unaffected. Using this strategy, the physical layer processing architecture in Software Defined Radio (SDR) systems can benefit from reduced complexity and increased design flexibility, as different waveform applications can be grouped into one part of a single FPGA. Waveform switching often means not only changing functionality, but also changing the FPGA clock frequency. However, that is beyond the current functionality of PR processes as the clock components (such as Digital Clock Managers (DCMs)) are excluded from the process of partial reconfiguration. In this paper, we present a novel architecture that combines another reconfigurable technology, Dynamic Reconfigurable Port (DRP), with PR based on a single FPGA in order to dynamically change both functionality and also the clock frequency. The architecture is demonstrated to reduce hardware utilization significantly compared with standard, static FPGA design
INTEGRAL timing and localization performance
Full text linkIn this letter we report on the accuracy of the attitude, misalignment, orbit
and time correlation which are used to perform scientific analyses of the
INTEGRAL data. The boresight attitude during science pointings has an accuracy
of 3 arcsec. At the center of the field, the misalignments have been calibrated
leading to a location accuracy of 4 to 40 arcsec for the different instruments.
The spacecraft position is known within 10 meters. The relative timing between
instruments could be reconstructed within 10 microsec and the absolute timing
within 40 microsec.Comment: 5 pages, 2 figures, accepted for publication in A+A letters, INTEGRAL
special issu
Time and Energy Efficient Matrix Factorization Using FPGAs
No full textAbstract. In this paper, new algorithms and architectures for matrix factorization are presented. Two fully-parallel and block-based designs for LU decomposition on configurable devices are proposed. A linear array architecture is employed to minimize the usage of long interconnects, leading to lower energy dissipation. The designs are made scalable by using a fixed I/O bandwidth independent of the problem size. High level models for energy profiling are built and the energy performance of many possible designs is predicted. Through the analysis of design tradeoffs, the block size that minimizes the total energy dissipation is identified. A set of candidate designs was implemented on the Xilinx Virtex-II to verify the estimates. Also, the performance of our designs is compared with that of state-of-the-art DSP based designs and with the performance of designs obtained using a state-of-the-art commercial compilation tool such as Celoxica DK1. Our designs on the FPGAs are significantly more time and energy efficient in both cases.
